Design Scheme of Embedded IP Video Phone Based on Network

introduction

Due to factors such as cost and quality of video communication, video phones have been neglected by users since its introduction until now. Now because of technological progress and the popularization of broadband Internet, videophones are showing new vitality. Industry experts predict that in the next few years, video phones will not only be able to interconnect with fixed-line telecommunications, PHS, mobile / Unicom mobile phones, but also with 3G mobile phones. Videophone will become an independent industry with good development prospects.

Based on a single 600 MHz TMS320DM643 (referred to as DM643) digital media processor from TI, I developed a set of embedded IP video phones with excellent performance and low prices to achieve real-time point-to-point network audio and video communication.

1 Hardware design based on TMS320DM643

DM643 digital media processor [1] integrates a series of peripherals to adapt to the development of video and imaging technology. It includes 3 configurable video ports, 1 10/100 Mbps Ethernet MAC (EMAC), 1 serial port for audio applications (McASP), 1 serial port (McBSP) and some other peripherals. There are 8 parallel processing units in the C64x core, using VLIW (Very Long Instruction Set) structure, processing capacity up to 4800MIPS, and 88 instructions are expanded on the basis of C6OOO common instruction set. These instructions enable C64x to more easily execute algorithms in image processing.

The composition of the embedded IP video phone based on a single DM643 is shown in Figure 1. The video signal input from the camera and the audio signal input from the microphone are sent to the DSP after A / D conversion. The DSP compresses, encodes, and merges the audio / video signal; then the data is transmitted through the local area network or the Internet, and from the network The received data is shunted, and the video signal is decoded and displayed and the audio signal is decoded and played separately. In the system, a keyboard is also connected through the McBSP / UART port of DM643 to realize the dialing function of the phone.

Figure 1: The composition of an embedded IP videophone

1.1 Video capture circuit

The video decoding chip used in this system is the SAA7l15 of Philips. The full TV signal input from the camera passes through clamping, anti-aliasing filtering, A / D conversion, YuV separation circuit inside the SAA7l15, in the conversion circuit of YuV to YCrCb Converted to BT.656 video data stream, input to the compression core unit DM643 through the video port VPo of DM643. The line / field synchronization signal of the video data is included in the EAV (End of AcTIve Video) and SAV (Startof AcTIve Video) time-base signals of the BT.656 digital video data stream. The video port only needs a video sampling clock and a sampling enable signal. SAA7l15 internal register parameter configuration and status read through 1 C bus. The principle of the video capture interface is shown in Figure 2.

Figure 2: The principle of the video capture port

DM643 sends the decoded video data to SAA7121 for display output through the video port VP1 channel. SAA7121 is a video coding chip of Philips, which can realize D / A conversion of digital video. The working mode of SAA7121 is determined by its internal control register, and the initialization of the control register is completed through the 1 C bus. DM643 uses its own 1 C bus module as the main controller to parameter control SAA7121.

1.3 Audio input / output circuit

This system uses TI's high-performance stereo codec TI V320AIC23 (referred to as AIC23) to achieve the collection and playback of audio signals. AIC23 is compatible with the DM643 I / 0 voltage and can be seamlessly connected to the DM643 McASP interface.

In this system, AIC23 works in the main mode, the sampling word width of the left and right channels are 16 bits. The data interface is in DSP mode. Set the working parameters and feedback status information of internal registers through the 12 C bus.

Due to the inherent characteristics of network transmission, audio data and video data cannot be uniform when transmitted to the receiver. If the sender does not make any corrections, it is difficult to guarantee the synchronized output of audio / video. In order to achieve sampling synchronization of audio and video, a phase-locked loop PI I 1708 is used. A 27 MHz clock is output from the UC pin of SAA7115, and the default clock frequency of 18.433 MHz is output via the SCKO 3 pin of PLI 1708 as the input master clock MCI of AIC23 The clock used in K.AIC23 can be obtained by dividing the main clock MCLK by setting the register. Since the audio and video sampling signals use the same clock source, there will be no problem of audio / video out of synchronization.